The Vortex 3.0 project, an open GPGPU based on the RISC-V instruction set architecture for parallel computing, has released a new version, which can be accessed here. This project is designed for use with the OpenCL API and the SIMT (Single Instruction, Multiple Threads) execution model. It can be utilized for research in 3D graphics and new GPU architecture development. Hardware blocks in Verilog, simulator, drivers, and design documentation are available under the Apache 2.0 license here.
The GPGPU is based on a standard RISC-V ISA, with additional instructions added to support GPU features and thread management. These changes to the instruction set architecture are minimal, with existing vector instructions being used whenever possible. Some of the additional instructions include “tex” for texture processing, vx_rast for rasterization control, and vx_rop for fragment handling. Various instructions are available to activate groups of threads running in parallel with the SIMD Engine. More information can be found here.
The evolving GPGPU now supports 32- and 64-bit RISC-V instruction set architectures RV32IMF and RV64IMAFD, with the option for shared memory, L1, L2, and L3 caches, as well as a customizable number of cores, warps, and threads. Each core has the ability to include various units such as ALUs, FPUs, LSUs, and SFUs. Xilinx and Altera FPGAs can be used to create prototypes, and simulation tools like Verilator, RTLSIM, and SimX can be employed to simulate the chip’s operation.
Application development is supported through a toolchain, which includes options for working with Vortex PoCL,