Coreboot 4.22, a free alternative to proprietary firmware and BIOS, has been released. The release of this project, which is distributed under the GPLV2 license, involved 135 developers who made 977 changes. Starting from the next issue, the project will switch to a new version naming convention that includes the date of release. For example, in February 2024, instead of version 4.23, the release will be named 24.02.00.
The main changes in Coreboot 4.22:
- The initial implementation of the AMD Opensil (Open-Source Silicon Initialization Library) platform, which simplifies firmware creation.
- Added support for 17 motherboards, 11 of which are used on devices with Chrome OS or on Google servers. The new motherboards include amd onyx, Intel Meteorlake-P RVP, Purism Librem 11, PURISM LIBREM L1UM V2, siemens fa ehl, and supermicro x11ssw-f.
- Added support for AMD Genoa SOC.
- Implemented support for the “.Data” section in the X86 architecture before memory initialization, allowing the use of global variables in the Code in the SI language. Data is placed in the cache using the Cache-AS-RAM (VMA) concept.
- Implemented support for the CBFS file system in X86 systems, allowing Coreboot components to be accommodated on Flash. The CBFS cache enables unpacking CBFS files without reserving a separate area of memory. Preram_cbfs_cache_Size and Ramstage_cbfs_cache_Size are used to configure the cache.
- Added the ability to embed Romstage into the bootable unit (BootBlock), reducing the code size by 10-20 thousand lines. This is particularly useful in configurations with VBOOT or Fallback-mode and for systems with limited loading units or slow loading carriers.
- Added API to GFX for detecting the presence of an external screen on devices with Intel chips.
- Implemented the ability to add a control amount for VBIOS in PCI_ROM when filling out the VFCT table. Some AMD drivers for Windows check this control amount.
- Added changes to enable launching Windows on
/Reports, release notes, official announcements.