is presented Project Release CoreBoot 4.14 , within which a free alternative is being developed with proprietary firmware and BIOS. The creation of the new version took part 215 developers who prepared 3660 changes.
Basic innovations :
- AMD CEZANNE initial support is implemented and a general reorganization of the code to support the SOC company AMD has been implemented. Unified typical code for AMD SOC, which allowed in code for AMD Cezanne to use the components that have already experienced for Soc Picasso.
- stabilized and is recognized as ready for work implements Support for Intel Xeon Scalable server processors ( Xeon-SP ) second and third generations – Skylake-SP (SKX-SP) and Cooperlake-SP (CPX-SP). The SKX-SP code is activated to support OCP Tiogapass motherboards, and CPX-SP – OCP Deltalake. Optimized and unified code base for supporting different generations XEON-SP.
- Added support for 42 motherboards, 25 of which is used on devices with Chrome OS or on Google servers. Among those not related to google boards:
- amd bilby and amd majolica;
- Gigabyte GA-D510UD;
- hp 280 g2;
- Intel Alderlake-M RVP, Intel Alderlake-M RVP, Intel Elkhartlake LPDDR4X CRB and Intel Shadowmountain;
- Kontron Come-Mal10;
- msi h81m-p33 (MS-7817 v1.2);
- Pine64 RockPro64;
- Purism Librem 14;
- System76 Darp5, Galp3-C, Gaze15, Oryp5 and Oryp6.
- supported support for motherboards Intel Cannonlake U LPDDR4 RVP, Intel Cannonlake U LPDDR4 RVP and Google Boldar.
- is a centralized ACPI GNVS framework, which is involved instead of APM_CNT_GNVS_UDPATE SMI handlers and is now used to initialize typical ACPI GNVS tables.
- Changed The format of the CBFS file system used to accommodate the Coreboot components on Flash. Changes reflected prepare for the implementation of the handy of individual files digital signatures.
/Media reports.